Bengali Wikipedia 10th Anniversary Celebration Kolkata/Submissions/Design and Implementation of High Speed Open Loop Comparator

Submission no.

Title of the submission

DESIGN AND IMPLEMENTATION OF HIGH SPEED OPEN LOOP COMPARATOR

Type of submission (discussion, hot seat, panel, presentation, tutorial, workshop)

Skype

Author of the submission

Deepa Talewad

E-mail address

ditalewad@gmail.com

Username

Country of origin

India.

Affiliation, if any (organisation, company etc.)

B.V.Bhoomaraddi College of Engg.,& Tech., Hubli, Karnataka, India.

Personal homepage or blog

Abstract (at least 300 words to describe your proposal)

Comparators are the basic building blocks in designing most of analog circuits in modern mixed mode signal system. The proposed PMOS based open loop comparator with low power dissipation, low offset, minimum delay and high speed is achieved. Comparators are basically used for comparison between two different or same electrical signals. The design of comparator becomes an important issue in analog circuit design[4] when technology scaled down. This paper describes about design and optimized layout[3] of open loop comparator used in high performance analog to digital converters employing parallel conversion stages.The performance of comparator is explained with their offset voltage, delay, speed and power. Accuracy of comparator is defined by its offset and power consumption, speed is keen interest for achieving overall higher performance ADC is defined by its delay[1]. In the proposed static comparator design inputs are configured from typical differential pair of comparator such that near equal current distribution seen at input transistors. This can be achieved by static open loop architecture described in this paper with two inputs are Vin as ramp signal varying between 0V to 1V with 500ns and Vref is 600mV constant voltage with capacitive load of 500fF. With these inputs with supply voltage of 1.8V with +/- 10% variation and quiescent current for overall design is 20µA. The simulation results of comparator gives an offset of 2mV[7] and delay of 20ns for different process corners and temperature range of -40°C to +125°C. The proposed open loop comparator design and optimized layout[5] is done using Cadence tool, UMC180 PDK in 180nm CMOS technology and occupies the active layout area of 41µm².

References:

1. Neeraj K. Chasta."A Very High Speed, High Resolution Current Comparator Design" ,International Journal of Electrical, Electronic Science and Engineering Vol:7 No:11, 2013.
2. Seong K. Hong [ I ] and Phillip E. Allen [21a]."Analog circuit layout with optimized performance",Oxford University Press, New York, 2002, Second Edition.
3. Alan Hasting "The Art of Analog Layout ",Pearson Education Asla limited and Tsinghua University Press.
4. Behzad Razavi "Design of Analog CMOS Integrated Circuits", Tata Mcgraw-Hill Edition 2002.
5. Dan Clein"CMOS IC Layout Concepts, Methodologies and Tools", Tata Mcgraw-Hill Edition 2002.
6. Vipul Katyal, Randall L. Geiger and Degang J. Chen, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs”, Dept. of Electrical and Computer Engineering Iowa State University Ames, Iowa, USA, IEEE APCCAS 2006.
7. Raghava Garipelly, “High Speed CMOS Comparator Design with 5mV Resolution”, International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013.

Track

Language of Track

English

Length of session (if other than 30 minutes, specify how long)

10 minutes

Will you attend Conference at Kolkata with own cost if your submission is not accepted?

Slides or further information (optional)

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