Bengali Wikipedia 10th Anniversary Celebration Kolkata/Submissions/Design of Voltage detector using P.O.R. circuit

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Submission no.
Title of the submission
Design of Voltage detector using P.O.R. circuit
Type of submission (discussion, hot seat, panel, presentation, tutorial, workshop)
Skype
Author of the submission
Sushma Suresh Sangolli
E-mail address
sssangolli@gmail.com
Username
Country of origin
India
Affiliation, if any (organisation, company etc.)
B.V.Bhoomaraddi College of Engg.,& Tech., Hubli, Karnataka, India.
Personal homepage or blog
Abstract (at least 300 words to describe your proposal)

A voltage detector circuit is designed to determine the presence or absence of required voltage range. In this paper voltage detector circuit is designed using POR circuit i.e. power on reset circuit. A power on reset circuit provides a reset signal when supply voltage ramps so the device starts to operate in known states [1]. The reset signal will be low when the supply voltage is rising and it will rapidly become high as soon as the supply voltage reaches the normal working voltage. The voltage detector is used in many battery powered applications like power fail indicator, low battery detection, etc. Voltage detector which uses power on reset circuit has sub-circuits like Schmitt trigger, delay elements, biasing circuit and cascaded current mirror [2]. Bias circuit consists of diode connected transistors and is used to reduce the overdrive voltage. The current mirror will mirror the current flowing through it, cascaded current mirror scales down the current so that current is in a subnano-ampere value, as long as it is in the saturation region so as to maintaining the required current (5µA) for the entire design. Delay circuit is used to delay the input ramp so as to get long reset time which must be given to Schmitt trigger [3]. Schmitt trigger is used to obtain the required threshold voltage by proper setting of upper switching point (1.2V) and lower switching point (0.6V) [4].Voltage detector circuit is designed for the following specifications input ramp from 0V to Vdd in 1ms or 1µs with supply voltage Vdd i.e. 1.8V with +/-10% variation, the threshold voltage detection range is from 0.6V to 1.2V, the temperature for which the design must work is from -40°C to 125°C, delay must be less than 20µs and the total current the design must consume must be less than 5µA. This design is implemented using Cadence tool UMC 180nm technology and simulated using Cadence environment. Simulation results shows that the required voltage range is detected for different process corners for temperature variation from -40°C to 125°C with total power consumption of 4.2µA and delay will be very less which can be neglected for input ramp from 0 to Vdd in 1ms but for input ramp from 0 to VDD in 1µs delay is 7ns.


References

  1. T. Yasuda, M. Yamamoto, and T. Nishi, “A power-on reset pulse generator”.
  2. Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee, and Seung-Tak Ryu "A Long Reset-Time Power-On Reset Circuit with Brown-Out Detection capability"' IEEEE TRANS A IEEE Transaction on Circuits and Systems refess brief RESS BRIEFS, VOL. 58, NO. 11, NOVEMBER 2011.
  3. S. U. Ay, “A nanowatt cascadable delay element for compact power-on reset (POR) circuits,” in Proc. 52nd IEEE Int. Midwest Symp. Circuits Syst., 2009, pp. 62–65.
  4. R. J. Baker, H. W. Li, and D. E. Boyce, “CMOS Design Layout and Simulation”. New York: Wiley-IEEE Press, 1997, pp. 355–362.
  5. S. K.Wadhwa, G. K. Siddhartha, and A. Gaurav, “Zero steady state current power on reset circuit with Brown-out detector,” in Proc. 19th Int. Conf. VLSID, 2006, pp. 631–636.
Track
Technology, Interface & Infrastructure
Language of Track
English
Length of session (if other than 30 minutes, specify how long)
Will you attend Conference at Kolkata with own cost if your submission is not accepted?
Slides or further information (optional)
Special requests


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